Temperature-compensation circuit techniques for high-density CMOS DRAMs

Temperature-compensation circuit techniques are presented for the CMOS DRAM internal voltage converter, the RC-delay circuit, and the back-bias generator, which do not need any additional process steps. The above-mentioned circuits have been designed and evaluated through a 16-Mb CMOS DRAM process. These circuits have shown an internal voltage converter (IVC) with an internal voltage temperature coefficient of 185 ppm/ degrees C, and an RC-delay circuit with a delay time temperature coefficient of 0.03%/ degrees C. As a result, a 6.5-ns faster RAS access time and improved latchup immunity have been achieved, compared with conventional circuit techniques.<
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