On the design of large receiver and transmitter arrays for OE-VLSI applications

The design environment, design and test flows, and the constraints and challenges of implementing large two-dimensional arrays of receiver and transmitter circuits for optoelectronic-very-large-scale-integration (OE-VLSI) applications is described, and the use of optically and electrically differential architectures is advocated. We show that the incorporation of design-for-testability features and chip-level test methodologies overcome some of the unique challenges of testing OE-VLSI receiver and transmitter circuits. We present design techniques that can be used to improve the switching-noise performance of fully differential OE-VLSI receiver and transmitter circuits. We show that the operational yield of large receiver arrays is maximized through the use of an optically and electrically differential architecture.