VLSI implementation of genetic four-step search for block matching algorithm

Genetic algorithm is well known for searching global optimum. It has been demonstrated its capability for block motion estimation with performance close to exhaustive full search using fewer search steps. However, it is computational expensive. A genetic four-step search is developed to alleviate the problem. It has a mean square error performance close to full search and much computational efficient than the traditional genetic algorithm. A FPGA implementation of the proposed algorithm is realized. The architecture is simple and suitable for valuable applications in the development of low cost multimedia products.