Energy-aware logic synthesis and technology mapping for MUX-based FPGAs

The paper is concerned with the widely addressed problem of logic synthesis and technology mapping for multiplexer based (MUX-based) Field-Programmable Gate Arrays (FPGAs). A novel approach for the synthesis of logic functions in terms of multiplexer based FPGAs (ACTEL like) has been presented in this paper. The logic functions are represented by decomposed Binary Decision Diagrams (BDDs). The approach comprises two basic steps-optimizing decomposed BDDs with the help of ratio-parameter based heuristic and then technology mapping of the optimized BDDs onto FPGA cells. Techniques like node duplication and sharing have been applied to minimize the number of FPGA cells and delay during technology mapping. Cell configurations have been chosen such that the switched capacitance and hence the power dissipation is minimized. The result, in terms of area, represented by the number of FPGA cells is comparable, but the performance in terms of delay and energy (power-delay product) are superior to the existing reported results.