Optimizing bipolar transistor performance in RF integrated circuits

Bipolar transistors of a 0.6 /spl mu/m BiCMOS technology were optimized for better performance in high-frequency circuits. First the lateral and vertical properties of the seven available devices were studied and the effects of scaling were examined. According to the available literature a summary was created about what parasitic elements could be found in the structures. After that some modifications were made on the layout of four devices to increase the cut-off frequency and the maximum frequency of oscillation. Special test patterns have been designed for on-wafer measurements. The post production testing was made by S-parameter measurements.