Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect

This paper reports an analysis of gate misalignment effect on the threshold voltage of double-gate ultrathin fully depleted (FD) silicon on insulator (SOI) NMOS devices using a compact model considering fringing electric field effect. Using the conformal mapping transformation approach, a closed-form compact model considering the fringing electric filed effect above the non-gate overlap region has been derived to provide an accurate prediction of the threshold voltage behavior as verified by the 2D simulation results.