A compact, low-power low-jitter digital PLL

This paper describes a compact, low-power and low-jitter digital PLL (DPLL). Digitizing the loop filter presents numerous challenges and advantages. In the proposed scheme, a wide-band DPLL is described that achieves low-jitter and low-power consumption. Low-jitter is achieved by using an all-digital adaptive bandwidth control scheme that can track the noise injected into the DPLL and optimize the loop bandwidth accordingly. A prototype DPLL employing has been implemented in a 0.25/spl mu/m CMOS technology. Measurement results show that jitter 130ps jitter is achieved at 144MHz. The area and power consumption outperform the traditional charge-pump based PLL by a factor of 3.5/spl times/ and 45% respectively.