Characterization of ultra-thin SOI transistors down to the 20 nm gate length regime with scanning spreading resistance microscopy (SSRM)

New device concepts have been introduced to fulfill the demands and scaling requirements of the International Technology Roadmap for Semiconductors (ITRS). This, in turn, increases the demands on the characterization methods, e.g. for the measurement of 2D-carrier profiles, which have to be improved to match. This article reports a comparative study of the electrical and analytical characterization of nanoscaled ultra-thin (UT) n-channel and p-channel SOI transistors. The devices were fabricated on 45 nm SOI with gate lengths as short as 20 nm. The gates were defined by electron-beam lithography and nanoscale dry etching. We use high resolution scanning spreading resistance microscopy (SSRM) to provide reliable information about the carrier profile and effective gate lengths of the devices. The results of these measurements are compared with electrical results and with high resolution TEM.