Modeling the fringing electric field effect on the threshold voltage of FD SOI nMOS devices with the LDD/sidewall oxide spacer structure

This paper presents analysis of the fringing electric field effect on the threshold voltage of fully depleted (FD) silicon-on-insulator nMOS devices with the lightly doped drain (LDD)/sidewall oxide spacer structure based on a closed-form analytical model derived from the two-dimensional (2-D) Poisson's equation and using the conformal mapping technique. Based on the analytical model, as verified by the experimental data and the 2-D simulation results, with a lower n-LDD doping density, the fringing electric field effect in the sidewall oxide spacer lowers the short-channel effect.