A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver

Time jitter in continuous-time ΣΔ modulators is a known limitation on the maximum achievable signal-to-noise-ratio (SNR). Analysis of time jitter in this type of converter shows that a switched-capacitor (SC) feedback digital-to-analog converter (DAC) reduces the sensitivity to time jitter significantly. An I and Q continuous-time fifth-order ΣΔ modulator with 1-bit quantizer and SC feedback DAC is presented, which demonstrates the improvement in maximum achievable SNR when using an SC instead of a switched-current (SI) feedback circuit. The modulator is designed for a GSM/CDMA2000/UMTS receiver and achieves a dynamic range of 92/83/72 dB in 200/1228/3840 kHz, respectively. The intermodulation distance IM2, 3 is better than 87 dB in all modes. Both the I and Q modulator consumes a power of 3.8/4.1/4.5 mW at 1.8 V. Processed in 0.18-μm CMOS, the 0.55-mm
²
integrated circuit includes a phase-locked loop, two oscillators, and a bandgap.