A 5-GHz CMOS front-end circuit with low power, low noise and variable gain for WLAN applications

Incorporating the low-IF architecture, a 5-GHz WLAN receiver front-end chip is implemented in a 0.18 /spl mu/m CMOS technology. The chip contains a single-in differential-out low noise amplifier with 1.5 dB noise figure (NF), 25 dB voltage gain and less than 13 mW power consumption, a folded structure downconversion mixer with 9.9 dB single side band noise figure (SSB NF), 13.7 dB voltage gain and+2.7 dBm IIP3, consuming 10 mA current under a 2V supply voltage. The chip also has a 12 dB gain adjustment through a VGA cell placed in parallel with LNA's input.