FPGA implementation of a deterministic bit-stream neuron

This paper presents a digital hardware implementation of a deterministic Bit-Stream Artificial Neuron (AN) with ten inputs. The design was made to be implemented in a FPGA device for a minimal hardware requirement. The simulation for XCV3200 Virtex FPGA device, showed the possibility to place around 200 neurons (including the extra logic required to run the networks). As each neuron has ten connections this means that it will be possible to place a network with 2000 weights.