Buffer stage for fast response LDO

The paper presents a buffer stage used in a fast response LDO processed in a double-metal 0.8 /spl mu/m CMOS process. The stage consists of a transconductance amplifier (OTA) in a unity-gain configuration. The buffer has a wideband architecture and is designed to drive the parasitic gate-to-source capacitance of the power transistor. Output impedance is lower than 2k/spl Omega/ and current consumption is less than 20/spl mu/A.