I/sub DDT/ ATPG based on ambiguous delay assignments

This paper introduces a new I/sub DDT/ test generation method based on the fact that a gate delay may differ from its nominal value. A Bayesian optimization algorithm based on genetic algorithms is utilized for I/sub DDT/ test generation. The paper proposes a fitness function to evaluate the evolution of the test patterns and uses a pseudo-probability method to create the first generation test patterns. The test patterns generated by the new approach are proved to be valid by a waveform simulator based on Boolean processes, even though gate delays are assigned randomly from 50% to 150% of their nominal values, and the number of the evolution generation can be reduced about 25%.