A BIST circuit for I/sub DDQ/ tests

In this paper, an I/sub DDQ/ test time reduction method is proposed which is suitable for BIST approaches. Also, a BIST circuit for I/sub DDQ/ tests, based on the method, is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performance is evaluated by SPICE simulation. The results show us that I/sub DDQ/ test time can be reduced by using this test circuit.