In-system failure investigation on 0.18 /spl mu/m high speed serial link ASIC using logic built-in self test

In this exciting chip debug investigation, a mysterious voltage sensitivity was exhibited in four out of six High Speed SerDes (HSS) serial link IP blocks on a 0.18 /spl mu/m prototype ASIC chip. A number of noise and circuit failure theories were hypothesized. The investigators conducted experiments in both the device manufacturing test and system verification card environment. Ultimately, the use of the at-speed logic built-in self test (LBIST) present in the HSS IP blocks exercised in the system environment allowed the team to crack the case.