Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 /spl mu/m CMOS

This paper presents a novel circuit architecture for the accurate realization of the basic 1.5-bit ADC stage common to switched capacitor algorithmic and pipelined ADCs. A floating buffer is proposed which enables the accurate addition of signal voltages without requiring precision components. 14-bit ADC linearity is demonstrated with uncharacterized metal-metal capacitors without the need for calibration or trimming. A prototype 12-bit 3.3 MS/s algorithmic ADC in 0.25 /spl mu/m standard CMOS is described. The power FOM is 1.2 pJ/conversion and the area FOM is 31 nm/sup 2//conversion - well below previously reported figures for algorithmic ADCs.