A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability

A simultaneous reconfigurable multi-chip access bus interface for application in high-bandwidth multi-drop parallel interconnections such as a memory bus has been developed. The interface utilizes a source synchronous signaling and direct-sequence code-division multiple access (CDMA) technique for high bus concurrency and low channel latency. The prototype chip, fabricated in 0.18-/spl mu/m CMOS and tested in a 10-cm test board achieves a data rate of 2 Gb/s/pin with multiple access and re-configurability between four (2-to-2) off-chip I/Os.