A sub-mW MPEG-4 motion estimation processor core for mobile video application

This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a gradient descent search algorithm combined with a sub block search method that reduces required computation power to 8 MOPS, maintaining high picture quality as equivalent as a full search method, and an optimized SIMD datapath architecture to decrease the clock frequency and operating voltage. It has been designed with CMOS 5-metal 0.18 /spl mu/m rules. The estimated power consumption to process a QCIF 15 fps video is less than 1 mW at 1.70 MHz at 1.0 V.