A test strategy for a bit-serial VLSI chip with analog I/O

A unique, one-bit-wide test bus was designed to assure random pattern testability of a bit-serial stereo signal processor chip with analog I/O. Analog circuitry was tested functionally and digital circuitry pseudorandomly, achieving very high fault coverage. Analysis of fault simulation results indicates better than 99.9% coverage of the datapath logic was achieved. These results were obtained from an approximate fault simulator that neglects the possibility of fault self-masking caused by reconvergent fanout. The use of this tool in particular cases is justified by circuit analysis using fault path (F-path) methods.<
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