Design of an integrated optical receiver in a standard CMOS process

This paper presents an integrated optical receiver that allows for the "last-mile" access needed in today's broadband networks. The circuit consists of an integrated photodetector, an amplification chain and a phase- and frequency-locked clock recovery system. It operates at a data rate of 155.52 Mbps with a sensitivity -20.45 dBm at a BER of 10/sup -10/ and was implemented in a 1.2/spl mu/m CMOS process. The circuit complies with relevant networking standard and synchronization of the data signal occurs within 1 /spl mu/s. The entire receiver consumes approximately 26.5 mW from a 3.3 V supply and occupies an area of 2.9 mm/sup 2/.