A universal test sequence for CMOS scan registers

A systematic method for analyzing all possible faults within the scan path of a scan-based CMOS circuit is given. The analysis shows that both logic and current monitoring are necessary in order to detect all irredundant faults. A universal test sequence is derived based on the analysis of single bridging faults. This sequence also detects all irredundant stuck-at and stuck-open faults. SPICE simulations show that CSM (current supply monitoring) method is an effective method for detecting some bridging faults.<
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