Memory system reliability improvement through associative cache redundancy

A redundancy memory architecture that increases system memory reliability without incurring the memory access speed degradation or size impact that result from using error-correction coding or paper-swapping techniques have been developed. The architecture uses a small associative cache memory to provide redundant memory locations. Logic is provided to perform memory system testing and remapping of fault memory locations. A VLSI circuit has been developed that incorporates the features of the architecture as a proof-of-concept demonstration. This device has been designated the memory reliability enhancement peripheral (MREP).<
>