A 25 MHz Viterbi FEC codec

An implementation of a single-chip Viterbi codec which incorporates many features into a single device is described. The device also implements a unified trellis decoder using the industry standard convolutional codes to achieve good coding gain using phase-shift keying (PSK) trellis encoding. The level of integration and the device speeds present a new upper bound on system performance based on convolutional coding systems. The device was produced by silicon-compiler-based tools in 15 months.<
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