A VLSI grammar processing subsystem for a real time large vocabulary continuous speech recognition system

The architecture and implementation of a grammar processing subsystem for a large vocabulary, real-time, continuous speech recognition system are summarized. This subsystem contains two custom VLSI chips which perform the evaluation of starting word probabilities associated with the across-word transitions in the hidden-Markov-model-based speech recognition system. This system has a maximum computation rate of 200 MOPS and an I/O bandwidth of 265 Mbyte/s. The recognized sentence is the sentence with the highest combined acoustic and language model probabilities.<
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