A low-power low-noise CMOS compatible 80 V subscriber line interface circuit

The design of a monolithic enhanced subscriber line interface circuit (ESLIC) is reported. Special care has been taken in the realization of the SLIC to achieve a low-power dissipation in both on-hook (70 mW) and off-hook (130 mW) line conditions. The intrinsic noise of the internal circuitry and the noise due to the exchange battery have been drastically reduced to achieve a total receive noise of -85 dBmp. The 80 V circuit covers all loop lengths for a widely variable exchange battery. The LSI is developed as an universal and flexible circuit using a 100 V 4 mu m merged bipolar, CMOS, DMOS technology (BCD). The LSI meets very stringent requirements on several specifications.<
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