A 300 K-circuit ASIC logic family CAD system

A computer-aided design (CAD) system has been developed to design CMOS application-specific integrated circuit (ASIC) logic family chips denser than any previously available, with performance comparable to bipolar technology. Design flow and key new features are described, and test chip results are given. Logic synthesis and transformation systems translate the designs to a technology-independent internal representation; optimize them for area, performance, and testability; and translate them to an implementation in the technology circuit library. The synthesis systems add logic circuits needed for testing and generate information about the clock trees used later in physical clock-free construction.<
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