Techniques for in-band phase noise reduction in /spl Delta//spl Sigma/ synthesizers

This paper reviews several techniques used to reduce the in-band phase noise contribution of /spl Delta//spl Sigma/ fractional-N frequency synthesizers. The paper develops several practical techniques for specifying the noise and linearity of components used in a /spl Delta//spl Sigma/ fractional-N synthesizer. As an example, it presents a synthesizer with an in-band phase noise floor of -97 dBc/Hz@10 KHz for an RF output frequency of 2.432 GHz and a reference frequency of 16 MHz. The synthesizer has a frequency resolution of 61 Hz and an on-chip crystal oscillator. The synthesizer was implemented in a 0.35-/spl mu/m SiGe process and consumes 6 mA from a 3 V supply. The in-band phase-noise, spurs, and power consumption of this synthesizer are each low and comparable to the state of the art.