On the analysis of /spl Delta//spl Sigma/ fractional-N frequency synthesizers for high-spectral purity

Since /spl Delta//spl Sigma/ Fractional-N synthesis is becoming a popular path to synthesizer integration, thorough analysis is mandatory to uncover its pitfalls. Two generic analysis methods for /spl Delta//spl Sigma/ fractional-N synthesis are presented. The first analysis method is based on linear system theory and provides insight on the fundamental bandwidth limitations imposed by the /spl Delta//spl Sigma/ quantization noise in terms of rms phase error and phase-noise. To swiftly and accurately examine the effect of nonidealities on the spectral purity of the synthesizer, a fast, nonlinear analysis method is developed. Serious in-band noise leakage and reemerging spurious tones can be observed, which are in close correspondence with experimental results. Both methods are applied to distinguish the pros and cons of multistage noise-shaping (MASH) and single-loop /spl Delta//spl Sigma/ modulators in fractional- N synthesis. Based on the analysis methods, practical circuit design guidelines are compiled, with a focus on monolithic /spl Delta//spl Sigma/ fractional-N synthesizer design in CMOS with high spectral purity. These circuit design guidelines are applied to design a monolithic /spl Delta//spl Sigma/-controlled fractional-N phased-locked loop in 0.25-/spl mu/m CMOS that complies to the stringent DCS-1800 cellular specifications, which serves as a test case for experimental verification of the presented analysis methods.