Low voltage/low power sub 50 nm double gate SOI ratioed logic

In this paper, we show how the approach can also be used to built NAND and XOR gates to create a complete logic family. This is the first report that proposes a unique building block for a comprehensive DG-SOI logic design style along with a gain in number of devices used without compromising the performance superiority. All simulations are done for 50 nm gate length devices using SILVACO tools.