Optimizing the salicide thickness for improving 130 nm PD SOI performances

The impact of an increased cobalt salicide thickness on MOS circuit performances for 130 nm node PD-SOI is analyzed. By adjusting the cobalt deposition thickness, low gate resistance, as well as better control of I/sub OFF/ for NMOS are achieved. Using devices and "circuits" results, it is shown that static current consumption is decreased by a factor 10 without compromising the dynamic performances, whereas the gate resistance is reduced by a factor 2-3 and the static noise margin for SRAM is improved by 10%.