Design of nanometer scale CMOS circuits

Summary form only given. The tremendous growth of the semiconductor industry is fueled by scaling of technology following Moore's law. However, as we enter the nanometer regime, leakage current is becoming one of the main concerns for designers. The circuit designers have to work hand in hand with device designers to deliver high-performance yet low-power and noise-tolerant systems. This talk considers different leakage mechanisms in nanometer scale devices and propose device architecture and circuit/CAD solutions for leakage-tolerant logic and memories for scaled technologies.