A low-jitter mutual-correlated pulsewidth control loop circuit

This work presents a low-jitter pulsewidth control loop (PWCL) circuit. A mutual-correlated scheme is implemented to adjust the duty cycle and increase the stability of the PWCL. The design is less sensitive to process variation. The jitter induced by voltage ripple is suppressed. The circuit is implemented using 0.35 /spl mu/m IP4M CMOS process. The area of the PWCL is 136/spl times/143 /spl mu/m/sup 2/. At an operating frequency of 300 MHz, the power dissipation and voltage ripple are reduced by 35.4% and 93.7%, respectively. A test chip is successfully verified to obtain 42 ps jitter at an operating frequency of 900 MHz.