Layout-aware gate-sizing and buffer insertion for low-power low-noise DSM circuits

Today's densely packed deep sub micron circuits operate at high frequencies, dissipate large amounts of power, and have simultaneous switching noise (SSN) in the power and ground networks. We propose an integrated gate-sizing and buffer insertion layout-aware approach to spread out the switching times of the gates in a circuit, and thus reduce SSN. We have efficiently formulated our problem as a linear programming one, achieving improvements of 12-14 %, on average, in the peak-peak current swing values over the original circuit implementations.