CMOS differential circuits using charge-redistribution and reduced-swing schemes [logic circuits]

Charge-redistribution low-swing differential logic (CLDL) circuits, are presented in this work. This logic can implement a complex function in a single gate. The CLDL circuit utilizes a charge-redistribution and reduced-swing scheme to reduce the power dissipation. In addition, a pipeline structure is formed by a series connection structure controlled by a true-single-phase clock, thereby achieving high-speed operation. A pipelined multiplier-accumulator (MAC) and an 8 bit synchronous counter, using the CLDL structure, were designed in a standard 0.35 /spl mu/m CMOS process.