A low power design approach for MOS current mode logic

In this paper, a closed form expression for the propagation delay of MOS current mode logic (MCML) is derived using simplified BSIM transistor equations. The expression shows the parameters that affect the delay. Based on the obtained expression, a design approach is devised that leads to minimum power dissipation in MOS current mode logic gates for a given gate delay and load. This approach can serve as the basis for an automated methodology to size power efficient MCML gates that are extensively used in integrated optical transceivers.