A 8192 complex point FFT/IFFT for COFDM modulation scheme in DVB-T system

In this paper, we propose an implementation method for a single-chip 8192 complex point FFT/IFFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 8 K complex data, a DRAM-based pipelined commutator architecture is used, and this brings 60% chip size reduction over the flip-flop approach. The 8192-point FFT/IFFT consists of cascaded blocks with six stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. For the IFFT operation, we a use control signal that changes the radix-4 butterfly operator and coefficients saved in ROM without additional blocks. The proposed FFT/IFFT architecture was fabricated using a 0.35 /spl mu/m standard CMOS process.