An area and power efficient RAKE receiver architecture for DSSS systems

In this paper, an area and power efficient RAKE receiver architecture is proposed for base and mobile-stations employing the direct sequence spread spectrum (DSSS) technique. One common parallel de-spreader provides precomputed sub-symbols to fingers for the proposed design, and, hence, each finger can operate at a lower clock speed to save power. Our simulation results indicate that the proposed RAKE architecture for a WCDMA system reduces power dissipation by 37% and the circuit complexity by 28% compared with that of a conventional RAKE receiver.