The reliability issues on ASIC/memory integration by SiP (system-in-package) technology

When integrating more than one chip in a package using so-called SiP (system-in-package) technology, the size reduction rate is approximately 30/spl sim/60% compared to the identical PCB (printed circuit board). In this paper, we review the advantages of using SiP first, and then some of the reliability issues are discussed, including leakage current, test, EMI (electromagnetic interference), EOS (electrical over stress) and latch-up, related to using SiP. Solutions to these reliabilities are proposed in this paper.