Modeling of radiation-induced leakage currents in CMOS/SOI devices

A new approach to model the effect of radiation-induced interface charges on silicon-on-insulator (SOI) devices has been implemented in a three-dimensional device simulation code. The model is validated by comparison of simulated and measured postradiation device characteristics. The applicability of the model is illustrated by analysis of standard and fully-depleted silicon-on-sapphire (SOS) devices. The results demonstrate and clarify the role of various bias conditions on parasitics in SOI structures and offer an explanation of the observed absence of back-channel conduction in fully-depleted nMOS-SOS transistors.<
>