Analysis and designing of the stable parallel packet switch

The parallel packet switch attracts a lot of attention from the communications equipment vendors since it can be practically applied into terabit switches and routers. In order to accelerate its recognition and deployment, we attempt to present the detailed analysis of stability for the parallel packet switch architecture. A model of the stable parallel packet switch (SPPS) is proposed. Then the constraints of traffic dispatch algorithms, the number of layers and internal speedup for the SPPS are theoretically analyzed. Based on these results an example of designing SPPS architecture with 1.28 T capacity is presented. Simulations were carried out to investigate the validity and practicality of the designed SPPS.