Prototype implementation and evaluation of a multibank embedded memory architecture in programmable logic

Advances in microelectronics fabrication technology have created new opportunities for system designers to employ embedded memory in system-on-chip (SoC) designs. This paper discusses a multibank embedded DRAM architecture and its prototype implementation in programmable logic. The architecture features a central memory controller with a request table that exploits concurrency among multiple banks and enables issuing requests and transferring responses in parallel. An implementation with four banks using an array size of 256/spl times/256 consumes 18% of the logic capacity in a Xilinx XCV2000E chip and 40% of the embedded SRAM memory blocks that are used to emulate DRAM storage. The functionality of our prototype implementation is verified with a logic analyzer.