Digital GaAs FET versus Si FET gate delay as predicted from the electron velocity

A FET model that takes into account the effective saturation velocity (including the effect of velocity overshoot), fringing capacitance, and source resistance is discussed. The model is applied to identical differential source-coupled FET logic gates in both GaAs and Si. The simulated gate delay of the Si logic gate is about 2.6 times that of the GaAs gate, thus refuting the common hypothesis that GaAs gate, thus refuting the common hypothesis that GaAs and Si delays should be about equal because their equilibrium saturated electron velocities are about equal.<
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