A 12 b 75 MS/s pipelined ADC using open-loop residue amplification

The multi-bit first stage of a 12 b 75 MS/s pipelined ADC uses an open-loop gain stage to achieve more than 60% residue amplifier power savings over a conventional implementation. Statistical background calibration removes linear and nonlinear residue errors in the digital domain. The prototype IC achieves 68.2 dB SNR, -76 dB THD, occupies 7.9 mm/sup 2/ in 0.35 /spl mu/m CMOS and consumes 290 mW at 3 V.