A 9/spl mu/W 50MHz 32b adder using a self-adjusted forward body bias in SoCs

This 32b adder in a 0.13/spl mu/m CMOS process consumes 9/spl mu/W at 50MHz and 0.3V and operates at 500MHz at 0.6V. Forward body biases are self-adjusted to minimize the threshold voltage and reduce PVT dependence. The power of the SoC can be reduced to 1/4 that of standard CMOS by gating the forward body bias in the IP blocks.