A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems

A 2.7 Gb/s interconnect transceiver chip-set based on Code Division Multiple Access (CDMA) is described and implemented in 0.18 /spl mu/m CMOS technology to achieve real-time system re-configurability and multiple I/O communication. The transceiver chip-set, with an Alexander-type multi-level data recovery circuit, can reconfigure multiple I/O signal routes within a symbol period of 0.8 ns. The chip-set dissipates 74 mW and occupies 0.3 mm/sup 2/ per I/O pair.