FPGA-based hardware architecture for neural networks: binary radix vs. stochastic

This paper is focused on the hardware implementation of neural networks. It describes the characteristics of two architectures designed to implement feed-forward fully connected artificial neural networks: the first FPGA prototype is based on traditional adders and multipliers of binary inputs, while the second takes advantage of stochastic representation of the inputs. The paper compares both prototypes using the time/spl times/area classic factor.