The integration of power supply components within standard cell integration circuits

The authors present aspects of the design of three standard-cell ASICs (application-specific integrated circuits). Each ASIC had an unusual power supply and I/O level requirement determined by its operating environment. The designs were completed using a highly automated procedure which included combining cells from Sierra's 1.5- mu m standard cell library with a few additional custom cells. The central core of each ASIC was constructed from the schematic by automatic place and route software and then surrounded by a ring of customized I/O and power management circuits. Through this method, the broad variety of available standard cells was employed, simulated, and operated in the 5.0-V CMOS electrical conditions for which they were originally designed. They were protected from the destructive stresses of the actual application of the ASICs by the custom cells. Two of the design examples are of on-chip voltage regulation with digital I/O level translation, and the third is an example of power supply extraction from the ASIC's TTL-compatible inputs, while eliminating the internal V/sub DD/ losses resulting from voltage drops of diode rectifiers.<
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