Electrical design rule checker for core and block based ASIC designs

Due to the complexity of ASIC (application-specific integrated circuit) designs, especially those containing core or block cells, it is necessary to perform automated design-rule checking on a netlist. An electrical design rule checker (EDRC) developed to perform design rule checks for conventional standard cells as well as core and block cells is described. Intel uses this tool as a part of accepting a netlist during the transfer of the design from the customer. The electrical design rule checker is described, with special emphasis on the core and block cell-specific checks.<
>