High performance CMOS dual-port SRAM compiler

A high-density, high-performance dual-port SRAM (static RAM) compiler has been developed with standard product features. The compiler can generate different SRAM configurations with a minimum of 512 bits up to a maximum of 9 kbits. The SRAM has a typical access time of 15 ns (1.5- mu m ASIC (application-specific integrated circuit) process) for the largest configuration (1 K words*9 bits or 512 words*18 bits). It is scalable to a 1- mu m ASIC process with a typical access time of 9 ns. The compiler takes only five min to generate a complete layout block, a transistor netlist, or a gate-level model netlist for any SRAM configuration.<
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